Output-Compensated Buffers with Source-Follower Input Structure and Image Capture Devices Using Same

ABSTRACT

An output-compensated buffer includes a buffer circuit that receives an input signal and produces an output signal responsive thereto at an output terminal, the buffer circuit including an input source-follower circuit that receives the input signal. A feedback circuit is connected to the output terminal and to the input source follower circuit and operative to vary an input capacitance of the source follower circuit responsive to the output signal at the output terminal. The input source follower circuit preferably includes a bias terminal coupled to a power source, and the feedback circuit is preferably capacitively coupled to the bias terminal. According to another aspect, an image capture device includes a charged coupled device (CCD) that generates a video signal. A buffer circuit is responsive to the CCD and operative to receives the video signal and produce an output signal responsive thereto at an output terminal, the buffer circuit including an input source-follower circuit that receives the video signal. A feedback circuit is connected to the output terminal and to the input source follower circuit and operative to vary an input capacitance of the source follower circuit responsive to the output signal at the output terminal.

CLAIM FOR PRIORITY AND RELATED APPLICATION

This application claims priority to and is a continuation of parentapplication Ser. No. 09/399,995, filed Sep. 20, 1999, the disclosure ofwhich is hereby incorporated herein by reference, and is related toKorean Patent Application No. 1998-39101, filed on Sep. 21, 1998, thecontents of which is also herein incorporated by reference in itsentirety.

FIELD OF THE INVENTION

The present invention relates to microelectronic devices, and moreparticularly, to signal buffers suitable for use in devices such ascharged-coupled device (CCD) image capture systems.

BACKGROUND OF THE INVENTION

Charge coupled devices (CCDs) are image capture devices that generallyoffer superior characteristics such as small size, light weight and lowpower consumption in comparison to other conventional image capturedevices. Accordingly, CCDs are commonly used in broadcasting or domesticvideo cameras, monitoring cameras, and digital still cameras.

As manufacturing and designing techniques have progressed, the densityof CCDs has generally increased, resulting in reduced size. As the sizeof CCDs has reduced, however, the levels of the signals produced by theimage capture elements in CCDs have generally become smaller. Therefore,it has become desirable to use output buffers with high gain to producesignals usable for video processing and other purposes from such weaksignals.

A typical output buffer is illustrated in FIG. 1. The output bufferincludes an input source follower circuit including respective drivingand load NMOS transistors M1, M2 which are biased between a power supplyvoltage VDD and a signal ground. An input signal, e.g., a signalproduced by a horizontal transfer section of a CCD image capture device,is applied to the gate terminal of the driving transistor M1, while acontrol signal Vg is applied to the gate terminal of the load transistorM2. A voltage produced on the source terminal of the driving transistorM1 is generated responsive to the input signal Vin, and is applied to asecond stage source follower circuit including driving and loadtransistors M3 and M4. The second stage source follower circuitsimilarly drives a third stage source follower circuit including drivingand load transistors M5, M6, producing an output signal Vout. Achievinghigh gain from such a circuit can be problematic.

SUMMARY OF THE INVENTION

In light of the foregoing, it is an object of the present invention toprovide buffers with high-gain, suitable for use with devices such asCCD image capture devices.

It is another object of the present invention to provide buffers havingsource follower input circuits.

These and other objects, features and advantages may be providedaccording to the present invention by output-compensated buffersincluding a buffer circuit that includes a input source followercircuit, and a feedback circuit that variably capacitively couples abias terminal of the input source follower to a power source, inresponse to the output of the buffer circuit. The feedback circuit isthus operative to vary the input capacitance of the buffer circuitresponsive to the output signal. According to one embodiment of thepresent invention, the feedback circuit comprises another sourcefollower circuit having an input that receives an output signal from thebuffer circuit and an output that is capacitively coupled to the biasterminal of the input source follower circuit.

In particular, according to an embodiment of the present invention, anoutput-compensated buffer includes a buffer circuit that receives aninput signal and produces an output signal responsive thereto at anoutput terminal, the buffer circuit including an input source-followercircuit that receives the input signal. A feedback circuit is connectedto the output terminal and to the input source follower circuit andoperative to vary an input capacitance of the source follower circuitresponsive to the output signal at the output terminal. The input sourcefollower circuit preferably comprises a bias terminal coupled to a powersource, and the feedback circuit is preferably capacitively coupled tothe bias terminal.

According to another embodiment of the present invention, the feedbacktransistor includes a first transistor having source terminal, a drainterminal connected to the power source, and a gate terminal connected tothe output terminal of the buffer circuit. The feedback circuit furtherincludes a second transistor having a drain terminal connected to thesource terminal of the first transistor at a signal node, a drainterminal connected to a signal ground and a gate terminal configured toreceive a control signal. A capacitor is coupled between the signal nodeand the bias terminal of the source follower circuit.

According to another aspect of the present invention, an image capturedevice includes a charged coupled device (CCD) that generates a videosignal. A buffer circuit is responsive to the CCD and operative toreceive the video signal and produce an output signal responsive theretoat an output terminal, the buffer circuit including an inputsource-follower circuit that receives the video signal. A feedbackcircuit is connected to the output terminal and to the input sourcefollower circuit and operative to vary an input capacitance of thesource follower circuit responsive to the output signal at the outputterminal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a conventional buffer with aninput source follower circuit.

FIG. 2 is a circuit diagram illustrating a CCD in combination with anoutput-compensated buffer according to an embodiment of the presentinvention.

FIG. 3 is a circuit diagram illustrating an output-compensated bufferaccording to an embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating an output-compensated bufferaccording to another embodiment of the present invention.

FIG. 5 is a circuit diagram of the output-compensate buffer of FIG. 4 incombination with a horizontal transfer section of a CCD.

FIGS. 6 a-6 b are waveform diagrams illustrating exemplary operations ofan output-compensated buffer according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. Like numbers refer to like elements throughout. It will beunderstood that when an element such as a layer, region or substrate isreferred to as being “on” another element, it can be directly on theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly on” another element,there are no intervening elements present. Moreover, each embodimentdescribed and illustrated herein includes its complementary conductivitytype embodiment as well.

FIG. 2 illustrates an image capture system 300 including a CCD imagecapture device 250 with a horizontal transfer section 200 and an outputcircuit including a reset transistor 120, connected to anoutput-compensated buffer 140, such as the output compensated buffers140, 140′ illustrated in FIGS. 3 and 4. The CCD image capture device 250includes a P type semiconductor substrate 201 having a surface coveredby an insulating layer 202. A plurality of transfer gate electrodes 204are formed on the insulating layer 202. Electrodes 204 on an insulatinglayer 202 form an array and are driven by multi-phase clock signals (asshown, 3 phase clock signals φ1, φ2, φ3). An output electrode 206 isalso formed on the insulating layer 202.

An N type floating diffusion region 208 is formed on the substrate 201near the output gate electrode 206. A reset gate electrode 212 is formedon the insulating layer 202 near the floating diffusion region 208, andanother N type impurity region 210 is formed on the substrate 201 nearthe reset gate electrode 212 such that the reset gate electrode 212 isdisposed between the floating diffusion region 208 and the N typeimpurity region 210. As a result, a channel is formed beneath the resetgate electrode 212, between the floating diffusion region 208 and the Ntype impurity region 210. The floating diffusion region 208, the N typeimpurity region 210 and the reset gate electrode 212 make up a resettransistor 120.

The three clock signals φ1, φ2, φ3 are respectively applied to thetransfer gate electrodes 204 such that a transfer well structure formedby the transfer gate electrodes 204 moves toward the output gateelectrode 206. The output gate electrode 206 receives gate signal VOG,while the reset gate electrode 212 receives reset signal φR The N typeimpurity region 210 is biased to a drain voltage VOD. The signals φ1,φ2, φ3, VOG, φR are applied to the transfer gate electrodes 204, theoutput gate electrode 206, the reset gate electrode 212 and the N typeimpurity region 210 to control charge transfer to and from the floatingdiffusion region 208. The floating diffusion region 208 is connected tothe output-compensated buffer 140, which buffers signals that aregenerated by transfer of charge to the floating diffusion region 208 bythe action of the electrodes 204, 206, producing output signals(voltages) Vout.

In order to convert weak charges into signals, the output-compensatedbuffer 140 preferably exhibits high gain. In order to achieve such highgain, it is desirable to reduce and preferably minimize the capacitanceat the diffusion region 208, which includes the input capacitance of theoutput-compensated buffer 140. For a charge injection of ΔQ, thevariation ΔV in voltage at the diffusion region 208 is given by:${{\Delta\quad V} = \frac{\Delta\quad Q}{Cs}},$

where Cs indicates the capacitance at the diffusion region 208. As canbe seen in the above formula, reducing the capacitance C increases thevoltage variation ΔV, and thus can improve sensitivity.

The relationship of capacitance of a signal source, such as the abovedescribed capacitance Cs of a CCD horizontal output section, connectedto an input source follower circuit may be related to the inputcapacitance C of the input source follower circuit itself and the gainA1 of the input source follower circuit by:C=(1−A1)Cs,where A1 has a value less than 1. As the input capacitance C of theinput source follower circuit is decreased, the gain A1 is increased,thus resulting in increased gain for the output buffer in which thesource follower circuit is used.

FIG. 3 illustrates an output-compensated buffer 140 according to anembodiment of the present invention. The output-compensated buffer 140includes a buffer circuit 7 and a feedback circuit 8. The buffer circuit7 includes an input terminal 2, an output terminal 4, a control terminal6, and a bias terminal N3. As illustrated, the buffer circuit 7 includesa single source follower circuit including first and second NMOStransistors M11 and M12. The first NMOS transistor M11 has a gateterminal that receives an input signal Vin at the input terminal 2 and asource terminal connected to the drain terminal of the second NMOStransistor M12. The first NMOS transistor M11 also has a drain terminalconnected to a resistor R1 at a node N3, with the resistor R1 also beingconnected to a power source VDD, such that a secondary power supplyvoltage VDD′ is applied to the drain terminal of the first NMOStransistor M11. The second NMOS transistor has a gate terminal thatreceives a control signal Vg applied at the control terminal 6 and asource terminal connected to a signal ground GND. In the source followerconfiguration shown, the first NMOS transistor M11 serves as a drivingtransistor, while the second NMOS transistor M12 serves as a loadtransistor.

The feedback circuit 8 includes another source follower circuit,including an NMOS transistor M13 with a source terminal connected to adrain terminal of an NMOS transistor M14 at a node N2. The NMOStransistor M13 has a drain terminal connected to the power source VDD,and a gate terminal that receives the output signal Vout produced by thebuffer circuit 7. The NMOS transistor M14 has a source terminalconnected to the signal ground GND and a gate terminal that receives thecontrol signal Vg. The node N2 of the feedback circuit 8 is capacitivelycoupled to the node N3 of the buffer circuit 7 by a capacitor C1. Thecapacitive coupling provided by the capacitor C1 allows AC (alternatingcurrent) components to be transferred to the power source VDD, whichreduces the input capacitance of the NMOS transistor M11 of the buffercircuit through a Miller effect. This can increase the AC gain of theoutput-compensated buffer 140.

FIG. 4 illustrates an output compensated buffer 140′ according toanother embodiment of the present invention. The output-compensatedbuffer 140′ includes a buffer circuit 7′ with an input terminal 2′, anoutput terminal 4′, a control terminal 6′ and a bias terminal N4. Thebuffer circuit 7′ has a 3-stage structure including an input sourcefollower circuit 14 and additional second and third stage sourcefollower circuits 10, 12. The input source follower circuit 14 includesdriving and load NMOS transistors M21, M22. A gate terminal of thedriving transistor M21 receives an input signal Vin applied at the inputterminal 2′, and has a source terminal connected to the drain terminalof the load transistor M22. The gate terminal of the load transistor M22receives a control signal Vg applied at the control input 6′. The drainterminal of the driving transistor is connected to one terminal of aresistor R2 at a node N4. The resistor R2 has a second terminalconnected at to a power source VDD, such that a secondary power supplyvoltage VDD′ is applied to the drain terminal of the driving transistorM21.

The second and third stage source follower circuits 12, 10 includerespective driving/load transistor pairs M19/M20, M17/M18. The gateterminal of the driving transistor M19 of the second stage sourcefollower circuit 12 is connected to the output of the input sourcefollower circuit 14, i.e., at the junction of the source and drainterminals of the driving and load transistors M21, M22. The drainterminal of the driving transistor M19 is connected to the power sourceVDD. The gate terminal of the driving transistor M17 of the third stagesource follower circuit 10 is connected to the output of the secondstage source follower circuit 12, at the junction of the source anddrain terminals of the driving and load transistors M19, M20. The drainterminal of the driving transistor M17 is connected to the power sourceVDD. The output of the third stage source follower circuit, i.e., thejunction of the source and drain terminals of the driving and loadtransistors M17, M18, is connected to the output terminal 4′, where theoutput signal Vout is produced.

The output compensated buffer 140′ is connected to a feedback circuit 8such as previously described with reference to FIG. 3. The capacitor C1of the feedback circuit 8 is connected to the first source followercircuit 14 and the gate of the transistor M13 of the feedback circuit 8is connected to the output of the third source follower circuit 10. Asthe components of the feedback circuit 8 have been described withreference to FIG. 3, they will not be discussed in further detail.

FIG. 5 is a schematic diagram illustrating the output-compensated buffer140′ of FIG. 4 in combination with a CCD horizontal transfer section 200and reset transistor 120. Charges supplied by the horizontal transfersection 200 are injected at the source terminal of the reset transistor120. The voltage Vin at the source terminal of the reset transistor 120is applied to the input source follower circuit 14 of the buffer circuit7′. As the components of the output buffer circuit 140′ have beenpreviously described with reference to FIG. 4, further detaileddescription of these components will not be provided.

Referring to FIG. 6 a, as the level of the input signal Vin increases,the voltage at the source terminal of the driving transistor M21increases proportionally to the input signal Vin. The voltage levelsproduced at the source terminals of the driving transistors M19 and M17of the second and third stage source follower circuits 12 and 10 alsoincrease proportionally to the voltages applied to their respective gateterminals, producing an output signal Vout that increases responsive toan increase in the input signal Vin. As shown in FIG. 6 b, the AC gainof the buffer circuit is boosted by the action of the capacitor C1 andthe feedback circuit 8, by boosting the effective bias voltage(secondary power supply voltage) VDD′ applied the drain terminal of thedriving transistor M21.

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being set forthin the following claims.

1. An output-compensated buffer, comprising: a buffer circuit thatreceives an input signal and produces an output signal responsivethereto at an output terminal, said buffer circuit including an inputsource-follower circuit that receives the input signal; and a feedbackcircuit having an input connected to said output terminal and an outputcapacitively connected to a bias terminal of said input source followercircuit and operative to vary an input capacitance of said sourcefollower circuit responsive to the output signal at said outputterminal.
 2. An output-compensated buffer according to claim 1, whereinsaid feedback circuit is operative to variably capacitively couple thebias terminal to the power source responsive to the output signal at theoutput terminal.
 3. An output-compensated buffer according to claim 1:wherein said source follower circuit comprises: a first transistorhaving a source terminal, a gate terminal configured to receive theinput signal, and a drain terminal connected to the power source througha resistor; and a second transistor having a drain terminal connected tothe source terminal of the first transistor, a source terminal connectedto a signal ground and a gate terminal configured to receive a controlsignal; and wherein said feedback circuit is coupled to the drainterminal of said first transistor.
 4. An output-compensated bufferaccording to claim 3, wherein said feedback circuit is capacitivelycoupled to the drain terminal of the first transistor.
 5. Anoutput-compensated buffer according to claim 4, wherein said feedbackcircuit is operative to variably capacitively couple the drain terminalof the first transistor to the power source responsive to the outputsignal at the output terminal.
 6. An output-compensated buffer accordingto claim 1, wherein the output terminal of the buffer circuit is anoutput terminal of the source follower circuit.
 7. An output-compensatedbuffer according to claim 1, wherein the buffer circuit furthercomprises a second source follower circuit connected to an output of theinput source follower circuit and operative to produce the output signalresponsive to the input signal applied to the input source followercircuit.
 8. An output-compensated buffer, comprising: a buffer circuitthat receives an input signal and produces an output signal responsivethereto at an output terminal, said buffer circuit including an inputsource-follower circuit that has an input terminal that receives theinput signal and a bias terminal that receives a bias voltage from apower source; and a feedback circuit connected to said output terminaland to said input source follower circuit and operative to variablycouple the power source and the bias terminal via a capacitor.
 9. Anoutput-compensated buffer according to claim 8: wherein said sourcefollower circuit comprises: a first transistor having a source terminal,a gate terminal configured to receive the input signal, and a drainterminal connected to the power source through a resistor; and a secondtransistor having a drain terminal connected to the source terminal ofthe first transistor, a source terminal connected to a signal ground anda gate terminal configured to receive a control signal; and wherein saidfeedback circuit is coupled to the drain terminal of said firsttransistor.
 10. An output-compensated buffer according to claim 8,wherein the output terminal of the buffer circuit is an output terminalof the source follower circuit.
 11. An output-compensated bufferaccording to claim 8, wherein the buffer circuit further comprises asource follower circuit connected to an output of the input sourcefollower circuit and operative to produce the output signal responsiveto the input signal applied to the input source follower circuit.
 12. Animage capture device, comprising: a charged coupled device (CCD) thatgenerates a video signal; a buffer circuit responsive to the CCD andoperative to receive the video signal and produce an output signalresponsive thereto at an output terminal, said buffer circuit includingan input source-follower circuit that receives the video signal; and afeedback circuit having an input connected to said output terminal andan output capacitively coupled to a bias terminal of said input sourcefollower circuit and operative to vary an input capacitance of saidsource follower circuit responsive to the output signal at said outputterminal.
 13. An image capture device according to claim 12, whereinsaid feedback circuit is operative to variably capacitively couple thebias terminal to the power source responsive to the output signal at theoutput terminal.